Circuit designs continue to become larger, requiring larger integrated circuits (ICs) for implementation. In some cases, a circuit design that can be implemented using a single, larger die can be implemented using an IC that includes two or more smaller dies. An IC that includes two or more smaller dies can be referred to as a “multi-die IC.” A multi-die IC is generally characterized as including two or more dies coupled to one another and placed within a single IC package. The circuit design is implemented across the multiple dies in lieu of using a single, larger die.
Multi-die ICs typically include physical traits that are not present within their single-die IC counterparts. For example, multi-die ICs can include Through Silicon Vias (TSVs). A TSV can be characterized as a vertical conductive path that extends completely through a die of the multi-die IC. Each TSV can electrically couple a node on a top surface of the die through which the TSV extends with a different node on a bottom surface of the same die.
Another example of a physical trait found within multi-die ICs is the physical coupling of dies. The individual dies of a multi-die IC are typically physically coupled together in some manner. For instance, the dies can be stacked or bonded.
These and other physical traits can induce stress within one or more of the dies of a multi-die IC. The stress, which is typically greater than the normalized stress that exists within a die of a conventional, single die IC, can detrimentally affect the performance of active devices implemented within the multi-die IC.